1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of inducing desired stress levels and stress profiles in the channel region of a transistor device by performing an ion implantation process and an anneal process on the gate electrode of the transistor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage (Vt) of the device, then there is no current flow through the device (ignoring undesirable leakage currents, which are hopefully relatively small). However, when the voltage applied to the gate electrode equal or exceeds the threshold voltage (Vt) of the device, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. During the fabrication of complex integrated circuit products using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors (NFET) and/or P-channel transistors (PFET), are formed on a substrate including a crystalline semiconductor layer.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure, etc. One particular technique that has been employed to increase the performance of transistor devices involves so-called stress memorization techniques (SMT) wherein certain types of stresses are induced in the channel region of the device to increase the charge carrier mobility of such devices. More specifically, channel stress engineering techniques are employed to create a tensile stress in the channel region for NFET transistors (to improve electron mobility) and to create a compressive stress in the channel region for PFET transistors (to increase hole mobility). The techniques employed in forming such nitride layers with the desired tensile stress or the desired compressive stress is well known to those skilled in the art.
In the case of stress engineering techniques that are performed on N-type transistors, the SMT process typically involves 1) forming a patterned mask layer that exposes the N-type transistors but covers any P-type transistors; 2) performing an amorphization implant process on the source/drain regions of the exposed N-type transistors or form regions of amorphous material in the source/drain regions; 3) removing the patterned mask layer; 4) forming a thin layer of silicon dioxide on the N-type transistors and the P-type transistors; 5) forming a specifically made tensile stress-inducing silicon nitride layer, an SMT layer, on the silicon dioxide layer, wherein the tensile stress-inducing silicon nitride layer is intended to impart a desired tensile stress in the channel regions of the N-type transistors; 6) performing a brief re-crystallization anneal process (e.g., 650° C. for about 10 minutes in a nitrogen ambient); and 7) in some cases, performing one or more etching steps to remove the stress-inducing silicon nitride layer and the thin layer of silicon dioxide. During the etching process that is performed to remove the tensile stress-inducing SMT layer, the thin silicon dioxide layer protects the substrate and the sidewall spacers formed adjacent the gate structures of the devices. During the re-crystallization anneal process, the amorphous silicon material in the source drain region is re-crystallized.
The present disclosure is directed to various methods of inducing desired stress levels and stress profiles in the channel region of a transistor device by performing an ion implantation process and an anneal process on the gate electrode of the transistor device that may improve the performance of the transistor device.